Multi-channel peripheral interface using selectively flaggable channel register sets for concurrent write in response to any selected channel register write instruction
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jul 13, 1993
Issued Date -
N/A
app pub date -
Dec 18, 1991
filing date -
Sep 14, 1988
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Each of the identical register sets associated with each of the multiple channels of a peripheral device includes an initialization register. Setting the appropriate bit in the initialization register of any one of the channels allows the data processing system serviced by the peripheral device to perform a concurrent write operation to the same selected register in each channel enabled for a concurrent write. The concurrent write operation is based on a standard write instruction and a standard system address.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully