Low power complementary MOSFET digital signal buffer circuit
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jul 20, 1993
Grant Date -
N/A
app pub date -
Oct 16, 1991
filing date -
Oct 16, 1991
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A low power complementary MOSFET buffer circuit includes an input complementary MOSFET inverter with a plurality of serially coupled diode-connected complementary MOSFETs and an output complementary MOSFET inverter. An input digital signal drives one of the input inverter's MOSFET gates, and passes through the diode-connected MOSFETs to be biased, or level-shifted, prior to driving the input inverter's other MOSFET gate. Driving the input inverter's MOSFET gates with both the input digital signal directly and its biased equivalent ensures that, when each of the input inverter's MOSFETs is turned 'off' in accordance with the logic level of the input digital signal, it is turned off more fully, thereby minimizing power dissipation. The inverted digital signal outputted from the input inverter drives both of the output inverter's MOSFET gates. The original input digital signal also drives one of the output inverter's MOSFET sources, whereby the low-to-high transition time of the output digital signal is reduced.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully