Cache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequence
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United States of America Patent
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Jul 20, 1993
Grant Date -
N/A
app pub date -
Feb 26, 1990
filing date -
Feb 26, 1990
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A system which integrates the multiple instruction queues and the branch target cache (BTC) of a high performance CPU design into a single physical structure. Effectively, the queues are merged into the BTC in such a manner that, at any point in time, most of this structure functions as a BTC while certain entries function as instruction queues. By using parts of the BTC to serve as instruction queues, the inefficiency of separate queue structures is eliminated and the queues are implemented with the greater device density characteristic of the RAM structure which the BTC core is based on. This merging of these structures also substantially simplifies the instruction queue control and the routing of instruction words between BTC entries and queues.
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