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Abstract

A configurable logic array includes an array of configurable logic cells arranged in columns and rows. A plurality of input/output cells are arranged around the perimeter of the array, and provide interfaces to input/output pads on the chip. A configurable interconnect structure includes vertical buses between the columns of configurable logic cells, and horizontal buses between the rows of configurable logic cells. Thus, each configurable logic cell in a subset of the array, has four adjacent buses in the interconnect structure. The configurable logic cells in this subset of the array include input structures, having programmable inputs connected to the buses on all four sides of the cell. Also, combinational logic connected to the input structure generates logic signals in response to the selected input signals. Finally, the configurable logic cells include output structures connected to the combinational logic, and having programmable outputs connected to the buses on all four sides of the cell.

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First Claim