Asynchronous glitchless digital MUX
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United States of America Patent
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Jul 27, 1993
Grant Date -
N/A
app pub date -
Sep 13, 1991
filing date -
Sep 13, 1991
priority date (Note) -
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Abstract
Circuit and method of glitchless switching between asynchronous data inputs to a digital multiplexer (MUX) by maintaining and conditioning the width of the clock pulse corresponding to a first data input signal so that an output pulse is produced having a pulse width that is never narrower than the narrowest of input signals, i.e., does not produce a narrow-pulse glitch. The circuit comprises select inputs in parallel to both a MUX via a select latch device and to an edge detector having an output pulse triggering a synchronization assembly. The synchronization assembly freezes the output in the last state received from the multiplexer. The select input edge detector freezes the original D0 input at a high state until the new input D1 is cleared through the synchronization assembly.
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