Plug contact with antifuse

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United States of America Patent

PATENT NO 5233217
SERIAL NO

07695363

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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An antifuse particularly suitable for submicron geometries is presented. The antifuse is formed between a silicon layer, which could be a doped region of the semiconductor substrate, an epitaxial layer or a polysilicon layer, and an upper metal interconnection layer. In contact holes in a silicon dioxide layer insulating the silicon and metal interconnection layers from each other, the antifuses have a thick refractory metal layer having a top surface approximately at the same level as the top surface of the insulating layer. Depending upon the process used to deposit the refractory metal layer, a thin adhesion layer may be located immediately below the refractory metal layer. Between the underlying silicon layer and upper interconnection layer, a thin semiconductor material layer of amorphous silicon may be located either below the refractory metal layer or above it. At its bottom, the interconnection layer also has a barrier layer to prevent any intermixing between the amorphous silicon layer and the metal interconnection layer.

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Patent Owner(s)

Patent OwnerAddress
CROSSPOINT SOLUTIONS INC5000 OLD IRONSIDES DRIVE SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Dixit, Pankaj San Jose, CA 17 1097
Holzworth, Monta R Santa Clara, CA 6 251
Ingram, III William P Los Altos, CA 6 251
Klein, Richard Mountain View, CA 38 757

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