Row redundancy for flash memories

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United States of America Patent

PATENT NO 5233559
SERIAL NO

07653786

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Abstract

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A method and apparatus for providing row redundancy in non-volatile semiconductor memories is disclosed. This method and apparatus provides for preconditioning of each row of memory cells prior to erasing the memory array, including any rows containing defective cells as well as any redundant rows.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BOULEVARD SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Brennan, Jr James Pilot Hill, CA 17 570

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