Multiport memory with test signal generating circuit controlling data transfer from RAM port to SAM port
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Aug 3, 1993
Grant Date -
N/A
app pub date -
Jun 10, 1991
filing date -
Jun 8, 1990
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
The disclosed semiconductor memory comprises a random access memory port, a serial access memory port, a data transfer gate formed between the two ports, and in particular a test signal generating circuit for generating a test signal to the data transfer gate to close the gate so that data stored in the serial access memory port can be read to outside, without transferring data from the random access memory port to the serial access memory port. Therefore, it is possible to discriminate an erroneous operation caused when data are read from the serial access memory port from that caused when data are transferred from the random access memory port to the serial access memory port.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully