Importance

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Abstract

The peripheral cache DASD subsystem is connected to predetermined host processors. A channel connection between the host processor and the peripheral subsystem has a much higher burst rate then the burst data transfer rate of a DASD while having an extended signal propagation time preventing rapid exchanges of interactive control signals. The branch write occurs in that data is written both to the DASD and to the cache simultaneously. The write domain is established in the subsystem by the host processor as a number of records to be written on the DASD only after the available cache space is compared with a needed cache space for the entire write domain. Whenever the available cache space is less than the write domain needs, then the peripheral cache DASD subsystem subsets the data transfer into a plurality of subset data transfers each having data storable in the available cache data storage space. Calculations for determining the maximum cache space are described and sets of machine operations are disclosed for effecting the above operations.

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First Claim