Multiprocessor type time varying image encoding system and image processor with memory bus control table for arbitration priority
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United States of America Patent
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Aug 17, 1993
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N/A
app pub date -
Sep 14, 1992
filing date -
May 10, 1989
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Abstract
A multiprocessor type time varying image encoding system having a plurality of digital signal processor (DSP) modules (DMM's) connected in parallel, each DMM having a DSP, a local memory and an interrupt control unit, a plurality of common memories for storing data which is being processed, parameters, etc., an input frame memory which enables reading and writing operations to be executed asynchronously, a combination of a task control unit and a task table for distributing tasks to the DMM's, a plurality of independent common buses, and a combination of a bus control unit and a bus control table for bus sharing control.
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