Vertical lead-on-chip package
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United States of America Patent
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Aug 24, 1993
Issued Date -
N/A
app pub date -
Feb 18, 1992
filing date -
Jan 14, 1991
priority date (Note) -
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Abstract
A vertical lead-on-chip package and the method of making defines a high density array of semiconductor devices with leads extending from and across one face of the device, to the edge of the device such that a plurality of devices are vertically mounted on a circuit board. Each device has a heat sink thereon which is held in a fixture which serves as an array heat sink during testing and burn-in and during mounting and operation of the devices on the circuit board.
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