Importance

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Abstract

An improved digital parallel correlator is disclosed. Illustratively, the inventive correlator utilizes a shift register which receives a signal comprising data bits encoded as chips. At each cycle of the signal, the chips in the shift register are compared to a reference sequence and the number of matches is obtained. Whenever the number of matches exceeds a fixed high threshold or falls below a fixed low threshold, indicating the presence of a binary 1 or binary 0 data bit, the chips in the shift register are set to a predetermined sequence such as the reference sequence or its complement. This amounts to correcting any chips of a bit that are received in error as soon as it is determined that the bit is a binary 1 or binary 0. This enables the high and low thresholds to be located as far as possible from the peak correlation values thereby increasing the number of chips that can be received in error.

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First Claim