Method for electroplating the lead pins of a semiconductor device pin grid array package
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Aug 31, 1993
Grant Date -
N/A
app pub date -
Aug 27, 1992
filing date -
Aug 27, 1991
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A method for manufacturing a pin grid array type semiconductor device package including a substrate having a principle surface and a bottom surface opposing the principal surface, a plurality of patterned metallized conductors formed in the substrate or on the principal surface of the substrate so as to be electrically connected to a semiconductor device chip to be located on the principal surface. A plurality of metallized pads are formed on the bottom surface and electrically connected to the patterned metallized conductors. A metal film is deposited so as to cover the bottom surface including the metallized pads, and a lead pin is soldered on the metal film above each metallized pad by a solder material. The lead pin is electroplated by applying a voltage to the metal film.
First Claim
Family
International Classification(s)
- [Classification Symbol]
- [Patents Count]
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully