Built-in test circuit connection for wafer level burnin and testing of individual dies

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United States of America Patent

PATENT NO 5241266
SERIAL NO

07866622

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ATTORNEY / AGENT: (SPONSORED)

Importance

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Abstract

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Integrated circuit devices are fabricated with an additional conductive layer deposited on a semiconductor wafer onto which the semiconductor devices have been formed. The additional layer provides a conductive path to power the test circuits and allows the use of very few electrical connections in order to permit testing of the devices while still on the wafer. The ability to test the devices while still on the wafer facilitates burning in the wafer prior to singulating the parts, since it is not necessary to establish electrical connections at contact points on the individual integrated circuit devices. In one embodiment of the invention, the additional conductive layer is a metal mask and in a further aspect of that embodiment permits external connections to be accomplished at locations outside the die areas, thereby avoiding damage to the integrated circuit devices. Subsequent to testing of the die in wafer form, the metal mask is stripped and the die may be singulated.

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Patent Owner(s)

Patent OwnerAddress
MICRON TECHNOLOGY INC8000 SOUTH FEDERAL WAY BOISE ID 83716-9632

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ahmad, Aftab Boise, ID 88 1851
Green, Robert S Boise, ID 19 830
Weber, Larren G Caldwell, ID 26 635

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