Apparatus for performing multiply and accumulate instructions with reduced power and a method therefor
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United States of America Patent
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Aug 31, 1993
Issued Date -
N/A
app pub date -
Jul 3, 1992
filing date -
May 6, 1991
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Abstract
An apparatus for performing multiplications with reduced power includes an arithmetic logic unit and a decode block for performing an equivalent of a multiply instruction. A frequently-encountered multiply instruction occurs between a variable and a known constant. If the known constant is positive or negative one, the decode block enables the arithmetic logic unit to either add the variable to zero, or subtract the variable from zero, in response to the sign bit of the known constant. In response to a multiply and accumulate instruction between a variable and a known constant of positive or negative one, the decode block enables the arithmetic logic unit to either add the variable to the prior accumulated result or to subtract it therefrom, in response to the sign bit of the known constant. In either case, the high-speed multiplier is disabled and its power saved.
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- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
- FREESCALE SEMICONDUCTOR, INC.
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Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Girardeau, Jr James W | Toulouse, FR | 13 | 366 |
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Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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