Importance

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Abstract

The present invention is directed to a programmable logic circuit used as an arbiter to control access to a shared resource, e.g. a system bus, by N devices in a computer system. The programmable arbiter according to the present invention, implements a logic design with sufficient flexibility to accommodate and selectively incorporate features of several different arbitration schemes including a straight priority scheme, a programmable arbitration, and a rotating priority arbitration scheme. In addition to these arbitration schemes, the arbiter of the present invention supports an extended programmable arbitration scheme whereby a device which is requesting access to the shared resource may be granted access to the resource even if it has used up its allocated share of bandwidth if there are no other devices requesting access to the shared resource. Furthermore, bus bandwidth may be allocated to particular device or to a group of devices at a particular priority level. In addition to providing for programmable allocation of bus bandwidth, the arbiter of the present invention permits the number of clock cycles allocated per bus window for one requesting device to be different from the number of clock cycles allocated per bus window for another device. In this manner, the size of the bus window can be designed to accommodate the individual requirements of each device permitting maximization of both the device's and the system's overall efficiency.

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First Claim