Importance

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Abstract

A hierarchical cache memory apparatus assembled in a multiprocessor computer system including a plurality of processors and a memory device, includes a plurality of first cache memory devices arranged in correspondence with the plurality of processors and each including a controller including a first status identification section for identifying status of each of a plurality of pieces of address information, a plurality of first connection devices for connecting the plurality of first cache memory devices in units of a predetermined number of devices to constitute a plurality of mini-cluster devices a plurality of second cache memory devices respectively connected to the first connection devices in correspondence with the plurality of mini-cluster devices, having all the addresses of address information of the plurality of first cache memory devices in the mini-cluster devices, and each comprising a controller including a second status identification section for identifying status of each of the plurality of address information, and a memory device connected to the second connection devices and having all the addresses of the plurality of address information of the plurality of second cache memory devices.

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First Claim