Low-power, standby mode computer
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United States of America Patent
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Aug 31, 1993
Issued Date -
N/A
app pub date -
Oct 9, 1992
filing date -
Jun 12, 1989
priority date (Note) -
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Abstract
A method and apparatus for configuring a computer in a low-power mode are provided. In the low-power mode, dynamic random access memory is refreshed by a battery powered system in order to maintain the memory contents. Low-power mode is entered by saving an interrupt mask and by disabling interrupts, followed by saving the DMA status, finishing DMA operations, and disabling DMA. After these steps, the I/O state of the machine is saved by saving various I/O registers and ports. A refresh of the memory is forced before the system refresh operations are discontinued.
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