Plasma treatment method and apparatus

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United States of America Patent

PATENT NO 5242539
SERIAL NO

07859336

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Abstract

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A plasma treatment method and apparatus utilize various gas inlet and outlet structure arrangements to optimize treatment characteristics for a semiconductor wafer. A buffer zone is created between gas inlets and the discharge zone of the vacuum treatment chamber to enhance uniformity of gas flow. The evacuation arrangement enables reactant gas to be exhausted uniformly to reduce gas residence time below a threshold while maintaining optimum flow rates and etch uniformity at low effective exhaust speeds.

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Patent Owner(s)

Patent OwnerAddress
RENESAS ELECTRONICS CORPORATIONTOKYO

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kanetomo, Masafumi Tokyo, JP 16 1082
Kobayashi, Junichi Ushiku, JP 164 4012
Kumihashi, Takao Kokubunji, JP 19 812
Mise, Nobuyuki Chiyodacho-inayoshi, JP 25 720
Tachi, Shinichi Sayama, JP 52 2828
Tsujimoto, Kazunori Higashi-yamato, JP 34 2259
Usui, Tatehito Ibaraki, JP 83 1626

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