Method and apparatus for fault tolerance
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United States of America Patent
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Sep 7, 1993
Grant Date -
N/A
app pub date -
Jun 25, 1990
filing date -
Jun 25, 1990
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method and apparatus for achieving fault tolerance in a computer system having at least a first central processing unit and a second central processing unit. The method comprises the steps of first executing a first algorithm in the first central processing unit on input which produces a first output as well as a certification trail. Next, executing a second algorithm in the second central processing unit on the input and on at least a portion of the certification trail which produces a second output. The second algorithm has a faster execution time than the first algorithm for a given input. Then, comparing the first and second outputs such that an error result is produced if the first and second outputs are not the same. The step of executing a first algorithm and the step of executing a second algorithm preferably takes place over essentially the same time period.
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