US Patent No: 5,243,703

Number of patents in Portfolio can not be more than 2000

Apparatus for synchronously generating clock signals in a data processing system

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Abstract

An apparatus for synchronously generating a first clock signal in a first circuitry and a second clock signal in a second circuitry of a data processing system is described. A clock generating circuitry generates a global clock signal. A transmission line transfers the global clock signal from its first end to its second end and includes a midpoint between the first end and the second end. A first clock signal generation circuit is coupled at a first point between the first end and the midpoint and a second point between the midpoint and the second end. The first and second points have the same line length to the midpoint. The first clock signal generation circuit generates the first clock signal at a first timing point which is halfway between the global clock signal with a first propagation delay from the first end to the first point and the signal with a second propagation delay from the first end to the second point. A second clock signal generation circuit is coupled at a third point between the first end and the midpoint and a fourth point between the midpoint and the second end. The third and fourth points have the same line length to the midpoint. The second clock signal generation circuit generates the second clock signal at a second timing point which is halfway between the global clock signal with a third propagation delay from the first end to the third point and the signal with a fourth propagation delay from the first end to the fourth point. The first timing point is the same as the second timing point such that the first signal is synchronized with the second signal.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
RAMBUS INC.LOS ALTOS, CA1206

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Farmwald, Michael Berkeley, CA 59 3717
Horowitz, Mark Menlo Park, CA 79 3782

Cited Art

Patent Info (Count) # Cites Year
 
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Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
ROUND ROCK RESEARCH, LLC (128)
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5,917,758 Adjustable output driver circuit 80 1996
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6,115,318 Clock vernier adjustment 71 1996
5,923,611 Memory having a plurality of external clock signal inputs 55 1996
5,838,177 Adjustable output driver circuit having parallel pull-up and pull-down elements 128 1997
6,912,680 Memory system with dynamic timing correction 34 1997
5,940,608 Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal 110 1997
5,920,518 Synchronous clock generator including delay-locked loop 112 1997
6,173,432 Method and apparatus for generating a sequence of clock signals 92 1997
5,953,284 Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same 82 1997
6,011,732 Synchronous clock generator including a compound delay-locked loop 201 1997
5,926,047 Synchronous clock generator including a delay-locked loop signal loss detector 67 1997
6,101,197 Method and apparatus for adjusting the timing of signals over fine and coarse ranges 134 1997
5,930,198 Memory having a plurality of external clock signal inputs 10 1997
5,886,948 Memory having a plurality of external clock signal inputs 37 1997
5,910,920 High speed input buffer 42 1997
6,269,451 Method and apparatus for adjusting data timing by delaying clock signal 43 1998
6,016,282 Clock vernier adjustment 216 1998
6,338,127 Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same 59 1998
6,349,399 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same 15 1998
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6,069,504 Adjustable output driver circuit having parallel pull-up and pull-down elements 68 1998
6,029,250 Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same 319 1998
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6,374,360 Method and apparatus for bit-to-bit timing correction of a high speed memory bus 32 1998
6,026,050 Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same 146 1999
6,201,424 Synchronous clock generator including a delay-locked loop signal loss detector 27 1999
6,326,810 Adjustable output driver circuit 46 1999
6,340,904 Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal 26 1999
6,084,434 Adjustable output driver circuit 49 1999
6,378,079 Computer system having memory device with adjustable data clocking 67 2000
6,327,196 Synchronous memory device having an adjustable data clocking circuit 53 2000
6,959,016 Method and apparatus for adjusting the timing of signals over fine and coarse ranges 13 2000
6,954,097 Method and apparatus for generating a sequence of clock signals 7 2001
6,801,989 Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same 53 2001
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6,477,675 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same 1 2001
6,437,600 Adjustable output driver circuit 43 2001
6,952,462 Method and apparatus for generating a phase dependent control signal 21 2001
6,662,304 Method and apparatus for bit-to-bit timing correction of a high speed memory bus 125 2002
6,643,789 Computer system having memory device with adjustable data clocking using pass gates 17 2002
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6,931,086 Method and apparatus for generating a phase dependent control signal 12 2002
7,016,451 Method and apparatus for generating a phase dependent control signal 4 2002
7,149,874 Memory hub bypass circuit and method 9 2002
6,647,523 Method for generating expect data from a captured bit pattern, and memory device using same 12 2002
7,245,145 Memory module and method having improved signal routing topology 10 2003
7,168,027 Dynamic synchronization of data capture on an optical or other high speed communications link 11 2003
7,120,727 Reconfigurable memory module and method 113 2003
7,428,644 System and method for selective memory module power management 44 2003
7,260,685 Memory hub and access method having internal prefetch buffers 31 2003
7,107,415 Posted write buffers and methods of posting write requests in memory modules 21 2003
7,389,364 Apparatus and method for direct memory access in a hub-based memory system 2 2003
7,210,059 System and method for on-board diagnostics of memory modules 67 2003
7,133,991 Method and system for capturing and bypassing memory transactions in a hub-based memory system 11 2003
7,085,975 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same 4 2003
7,136,958 Multiple processor system and method including multiple memory hub modules 31 2003
7,310,752 System and method for on-board timing margin testing of memory modules 5 2003
7,194,593 Memory hub with integrated non-volatile memory 36 2003
7,159,092 Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same 4 2003
7,120,743 Arbitration system and method for memory responses in a hub-based memory system 47 2003
7,181,584 Dynamic command and/or address mirroring system and method for memory modules 36 2004
7,120,723 System and method for memory hub-based expansion bus 23 2004
7,213,082 Memory hub and method for providing memory sequencing hints 17 2004
6,980,042 Delay line synchronizer apparatus and method 45 2004
7,162,567 Memory hub and method for memory sequencing 33 2004
7,180,522 Apparatus and method for distributed memory control in a graphics processing system 5 2004
7,242,213 Memory module and method having improved signal routing topology 9 2004
7,249,236 Method and system for controlling memory accesses to memory modules having a memory hub architecture 3 2004
7,047,351 Memory hub bypass circuit and method 42 2005
7,222,197 Apparatus and method for direct memory access in a hub-based memory system 3 2005
7,415,404 Method and apparatus for generating a sequence of clock signals 3 2005
7,418,071 Method and apparatus for generating a phase dependent control signal 7 2005
7,282,947 Memory module and method having improved signal routing topology 8 2005
7,605,631 Delay line synchronizer apparatus and method 4 2005
7,373,575 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same 1 2006
7,415,567 Memory hub bypass circuit and method 2 2006
7,222,210 System and method for memory hub-based expansion bus 6 2006
7,206,887 System and method for memory hub-based expansion bus 38 2006
7,174,409 System and method for memory hub-based expansion bus 7 2006
7,418,526 Memory hub and method for providing memory sequencing hints 25 2006
7,490,211 Memory hub with integrated non-volatile memory 0 2006
7,251,714 Method and system for capturing and bypassing memory transactions in a hub-based memory system 6 2006
7,689,879 System and method for on-board timing margin testing of memory modules 4 2006
7,529,896 Memory modules having a memory hub containing a posted write buffer, a memory device interface and a link interface, and method of posting write requests in memory modules 1 2006
7,437,579 System and method for selective memory module power management 37 2006
7,278,060 System and method for on-board diagnostics of memory modules 2 2006
7,412,566 Memory hub and access method having internal prefetch buffers 14 2006
7,386,649 Multiple processor system and method including multiple memory hub modules 15 2006
7,353,320 Memory hub and method for memory sequencing 2 2006
7,644,253 Memory hub with internal cache and/or memory access prediction 1 2006
8,181,092 Dynamic synchronization of data capture on an optical or other high speed communications link 0 2006
7,546,435 Dynamic command and/or address mirroring system and method for memory modules 0 2007
7,370,134 System and method for memory hub-based expansion bus 23 2007
7,716,444 Method and system for controlling memory accesses to memory modules having a memory hub architecture 3 2007
7,889,593 Method and apparatus for generating a sequence of clock signals 0 2007
7,516,363 System and method for on-board diagnostics of memory modules 4 2007
7,557,601 Memory module and method having improved signal routing topology 2 2007
7,581,055 Multiple processor system and method including multiple memory hub modules 3 2007
7,818,712 Reconfigurable memory module and method 0 2008
7,562,178 Memory hub and method for memory sequencing 1 2008
7,610,430 System and method for memory hub-based expansion bus 9 2008
7,657,813 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same 1 2008
7,966,430 Apparatus and method for direct memory access in a hub-based memory system 0 2008
7,602,876 Method and apparatus for generating a phase dependent control signal 5 2008
8,127,081 Memory hub and access method having internal prefetch buffers 0 2008
7,913,122 System and method for on-board diagnostics of memory modules 0 2008
7,945,737 Memory hub with internal cache and/or memory access prediction 0 2009
7,975,122 Memory hub with integrated non-volatile memory 0 2009
7,746,095 Memory module and method having improved signal routing topology 2 2009
7,873,775 Multiple processor system and method including multiple memory hub modules 0 2009
8,107,580 Method and apparatus for generating a phase dependent control signal 1 2009
8,164,375 Delay line synchronizer apparatus and method 0 2009
7,899,969 System and method for memory hub-based expansion bus 0 2009
7,954,031 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same 0 2009
7,958,412 System and method for on-board timing margin testing of memory modules 3 2010
7,908,452 Method and system for controlling memory accesses to memory modules having a memory hub architecture 0 2010
7,966,444 Reconfigurable memory module and method 0 2010
8,244,952 Multiple processor system and method including multiple memory hub modules 0 2011
8,086,815 System for controlling memory accesses to memory modules having a memory hub architecture 1 2011
8,195,918 Memory hub with internal cache and/or memory access prediction 0 2011
8,209,445 Apparatus and method for direct memory access in a hub-based memory system 0 2011
8,200,884 Reconfigurable memory module and method 2 2011
8,117,371 System and method for memory hub-based expansion bus 0 2011
8,234,479 System for controlling memory accesses to memory modules having a memory hub architecture 0 2011
8,433,023 Method and apparatus for generating a phase dependent control signal 0 2012
 
MOSAID TECHNOLOGIES INCORPORATED (72)
5,946,244 Delay-locked loop with binary-coupled capacitor 121 1997
6,510,503 High bandwidth memory interface 168 1998
6,400,641 Delay-locked loop with binary-coupled capacitor 3 1999
6,262,921 Delay-locked loop with binary-coupled capacitor 46 2000
6,256,259 Delay-locked loop with binary-coupled capacitor 0 2000
6,483,757 Delay-locked loop with binary-coupled capacitor 1 2001
6,490,224 Delay-locked loop with binary-coupled capacitor 9 2001
6,490,207 Delay-locked loop with binary-coupled capacitor 22 2001
6,779,097 High bandwidth memory interface 44 2002
7,299,330 High bandwidth memory interface 35 2004
7,599,246 Delay locked loop implementation in a synchronous dynamic random access memory 0 2005
7,652,922 Multiple independent serial link memory 2 2005
8,364,861 Asynchronous ID generation 0 2006
7,515,471 Memory with output control 12 2006
8,069,328 Daisy chain cascade configuration recognition technique 0 2006
7,818,464 Apparatus and method for capturing serial input data 0 2006
7,529,149 Memory system and method with serial and parallel modes 2 2006
7,747,833 Independent link and bank selection 2 2006
8,271,758 Apparatus and method for producing IDS for interconnected devices of mixed type 2007
8,010,709 Apparatus and method for producing device identifiers for serially interconnected devices of mixed type 0 2007
7,551,492 Non-volatile semiconductor memory with page erase 54 2007
8,331,361 Apparatus and method for producing device identifiers for serially interconnected devices of mixed type 0 2007
8,010,710 Apparatus and method for identifying device type of serially interconnected devices 1 2007
7,853,727 Apparatus and method for producing identifiers regardless of mixed device type in a serial interconnection 1 2007
7,802,064 Flash memory system control scheme 1 2007
8,335,868 Apparatus and method for establishing device identifiers for serially interconnected devices 0 2007
8,086,785 System and method of page buffer operation for memory devices 0 2007
7,688,652 Storage of data in memory via packet strobing 1 2007
7,904,639 Modular command structure for memory and memory system 9 2007
8,122,202 Reduced pin count interface 0 2007
8,266,372 High bandwidth memory interface 0 2007
8,250,297 High bandwidth memory interface 0 2007
7,765,376 Apparatuses for synchronous transfer of information 0 2007
7,836,340 Methods and systems for failure isolation and data recovery in a configuration of series-connected semiconductor devices 2 2007
7,817,470 Non-volatile memory serial core architecture 5 2007
7,991,925 Apparatus and method for identifying device types of series-connected devices of mixed type 0 2008
7,751,272 Semiconductor device and method for selection and de-selection of memory devices interconnected in series 0 2008
7,913,128 Data channel test apparatus and method thereof 1 2008
8,046,527 Apparatus and method for using a page buffer of a memory device as a temporary cache 0 2008
7,774,537 Apparatus and method of page program operation for memory devices with mirror back-up of data 5 2008
7,885,140 Clock mode determination in a memory system 4 2008
7,796,462 Data flow control in multiple independent port 2 2008
7,940,572 NAND flash memory having multiple cell substrates 0 2008
8,139,390 Mixed data rates in memory devices and systems 0 2008
7,719,892 Flash memory device with data output control 2 2008
7,983,099 Dual function compatible non-volatile memory device 0 2008
7,826,294 Memory with output control 2 2008
8,037,235 Device and method for transferring data to a non-volatile memory device 0 2008
7,957,173 Composite memory having a bridging device for connecting discrete memory devices to a system 1 2009
8,169,849 Memory system and method with serial and parallel modes 0 2009
7,872,921 Non-volatile semiconductor memory with page erase 1 2009
8,134,852 Bridge device architecture for connecting discrete memory devices to a system 2 2009
8,369,182 Delay locked loop implementation in a synchronous dynamic random access memory 0 2009
8,194,481 Semiconductor device with main memory unit and auxiliary memory unit requiring preset operation 0 2009
8,144,528 Memory with data control 0 2010
8,000,144 Method and system for accessing a flash memory device 1 2010
7,945,755 Independent link and bank selection 0 2010
7,908,429 Apparatus and method of page program operation for memory devices with mirror back-up of data 0 2010
8,159,893 Data flow control in multiple independent port 1 2010
8,289,805 Non-volatile memory bank and page buffer therefor 1 2010
8,199,598 Memory with output control 1 2010
7,995,401 Non-volatile semiconductor memory with page erase 1 2010
8,195,839 Apparatus and method for producing identifiers regardless of mixed device type in a serial interconnection 0 2010
8,432,767 Clock mode determination in a memory system 0 2011
8,060,691 Apparatus and method of page program operation for memory devices with mirror back-up of data 0 2011
8,392,767 Data channel test apparatus and method thereof 0 2011
8,285,960 Independent link and bank selection 0 2011
8,270,244 Dual function compatible non-volatile memory device 0 2011
8,230,129 Apparatus and method for identifying device types of series-connected devices of mixed type 2011
8,213,240 Non-volatile semiconductor memory with page erase 0 2011
8,363,444 Bridge device architecture for connecting discrete memory devices to a system 0 2012
8,427,897 Memory with output control 0 2012
 
MICRON TECHNOLOGY, INC. (47)
7,941,056 Optical interconnect in high-speed memory systems 2 2001
7,200,024 System and method for optically interconnecting memory devices 22 2002
7,117,316 Memory hub and access method having internal row caching 14 2002
7,254,331 System and method for multiple bit optical data transmission in memory systems 10 2002
6,944,743 Memory hub bypass circuit and method 0 2002
7,836,252 System and method for optimizing interconnections of memory devices in a multichip module 1 2002
6,937,057 Memory module and method having improved signal routing topology 0 2003
7,366,920 System and method for selective memory module power management 0 2003
7,234,070 System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding 13 2003
7,137,024 System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding 0 2003
7,330,992 System and method for read synchronization of memory modules 4 2003
7,188,219 Buffer control system and method for a memory system having outstanding read and write request buffers 34 2004
7,788,451 Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system 10 2004
7,412,574 System and method for arbitration of memory responses in a hub-based memory system 14 2004
7,257,683 Memory arbitration system and method having an arbitration packet protocol 7 2004
7,447,240 Method and system for synchronizing communications links in a hub-based memory system 3 2004
7,590,797 System and method for optimizing interconnections of components in a multichip memory module 1 2004
7,222,213 System and method for communicating the synchronization status of memory modules during initialization of the memory modules 31 2004
7,363,419 Method and system for terminating write commands in a hub-based memory system 30 2004
7,519,788 System and method for an asynchronous data buffer having buffer write and read pointers 4 2004
7,310,748 Memory hub tester interface and method for use thereof 9 2004
7,106,611 Wavelength division multiplexed memory module, memory system and method 20 2004
7,392,331 System and method for transmitting data packets in a computer system having a memory hub architecture 7 2004
7,289,347 System and method for optically interconnecting memory devices 7 2005
7,272,682 Memory hub bypass circuit and method 0 2006
7,870,329 System and method for optimizing interconnections of components in a multichip memory module 2 2006
7,594,088 System and method for an asynchronous data buffer having buffer write and read pointers 1 2006
7,805,586 System and method for optimizing interconnections of memory devices in a multichip module 2 2006
7,596,641 System and method for transmitting data packets in a computer system having a memory hub architecture 1 2006
7,489,875 System and method for multiple bit optical data transmission in memory systems 1 2006
7,434,081 System and method for read synchronization of memory modules 1 2006
7,266,633 System and method for communicating the synchronization status of memory modules during initialization of the memory modules 8 2006
7,529,273 Method and system for synchronizing communications links in a hub-based memory system 3 2006
7,461,286 System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding 5 2006
7,411,807 System and method for optically interconnecting memory devices 2 2006
7,382,639 System and method for optically interconnecting memory devices 1 2006
7,412,571 Memory arbitration system and method having an arbitration packet protocol 7 2007
7,823,024 Memory hub tester interface and method for use thereof 1 2007
7,774,559 Method and system for terminating write commands in a hub-based memory system 9 2007
8,082,404 Memory arbitration system and method having an arbitration packet protocol 0 2008
8,392,686 System and method for read synchronization of memory modules 0 2008
7,949,803 System and method for transmitting data packets in a computer system having a memory hub architecture 0 2009
8,239,607 System and method for an asynchronous data buffer having buffer write and read pointers 0 2009
8,291,173 Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system 0 2010
8,190,819 System and method for optimizing interconnections of memory devices in a multichip module 0 2010
8,438,329 System and method for optimizing interconnections of components in a multichip memory module 0 2011
8,346,998 System and method for transmitting data packets in a computer system having a memory hub architecture 0 2011
 
RAMBUS INC. (27)
5,390,308 Method and apparatus for address mapping of dynamic random access memory 156 1992
5,511,024 Dynamic random access memory system 74 1994
5,430,676 Dynamic random access memory system 113 1994
5,434,817 Dynamic random access memory system 26 1994
6,370,668 High speed memory system capable of selectively operating in non-chip-kill and chip-kill modes 43 1999
RE39879 Method of transferring data by transmitting lower order and upper order memory address bits in separate words with respective op codes and start information 0 2000
6,842,864 Method and apparatus for configuring access times of memory devices 31 2000
7,313,639 Memory system and device with serialized data transfer 10 2003
7,237,048 Memory system and device with serialized data transfer 0 2003
6,826,663 Coded write masking 15 2003
7,039,782 Memory system with channel multiplexing of multiple memory devices 8 2003
7,171,528 Method and apparatus for generating a write mask key 6 2004
7,574,616 Memory device having a power down exit register 1 2004
7,161,400 Phase synchronization for wide area integrated circuits 0 2004
8,127,152 Method of operation of a memory device and system including initialization at a first frequency and operation at a second frequency and a power down exit mode 1 2004
7,571,330 System and module including a memory device having a power down mode 1 2005
7,581,121 System for a memory device having a power down mode and method 31 2005
7,464,225 Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology 43 2005
7,729,151 System including a buffered memory module 1 2006
7,478,181 Memory system and device with serialized data transfer 0 2006
7,932,755 Phase synchronization for wide area integrated circuits 0 2007
7,562,271 Memory system topologies including a buffer device and an integrated circuit memory device 8 2007
7,526,597 Buffered memory having a control bus and dedicated data lines 8 2007
7,523,248 System having a controller device, a buffer device and a plurality of memory devices 4 2008
7,925,808 Memory system and device with serialized data transfer 0 2008
7,685,364 Memory system topologies including a buffer device and an integrated circuit memory device 2 2009
8,108,607 Memory system topologies including a buffer device and an integrated circuit memory device 0 2010
 
MOSYS, INC. (12)
5,655,113 Resynchronization circuit for a memory system and method of operating same 146 1994
5,613,077 Method and circuit for communication between a module and a bus controller in a wafer-scale integrated circuit system 75 1994
5,498,990 Reduced CMOS-swing clamping circuit for bus lines 129 1995
5,737,587 Resynchronization circuit for circuit module architecture 18 1995
5,666,480 Fault-tolerant hierarchical bus system and method of operating same 106 1995
5,592,632 Defect tolerant integrated circuit subsystem for communication between a module and a bus controller in a wafer-scale integrated circuit system 93 1995
5,831,467 Termination circuit with power-down mode for use in circuit module architecture 87 1996
5,843,799 Circuit module redundancy architecture process 58 1997
6,272,577 Data processing system with master and slave devices and asymmetric signal swing bus 19 1997
6,483,755 Memory modules with high speed latched sense amplifiers 56 2001
6,717,864 Latched sense amplifiers as high speed memory in a memory system 1 2002
7,634,707 Error detection/correction method 0 2004
 
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6,160,423 High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines 117 1998
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6,327,205 Signal latching of high bandwidth DRAM arrays when skew between different components is higher than signal rate 58 2000
6,513,080 High speed bus system and method for using voltage and timing oscillating references for signal detection 52 2000
6,812,767 High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines 1 2001
7,123,660 Method and system for deskewing parallel bus channels to increase data transfer rates 8 2002
7,009,428 High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines 0 2004
7,190,192 High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines 0 2005
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TEXAS INSTRUMENTS INCORPORATED (8)
6,223,264 Synchronous dynamic random access memory and data processing system using an address select signal 1 1994
5,587,954 Random access memory arranged for operating synchronously with a microprocessor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock 23 1994
5,808,958 Random access memory with latency arranged for operating synchronously with a micro processor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock 12 1995
5,982,694 High speed memory arranged for operating synchronously with a microprocessor 0 1996
6,115,321 Synchronous dynamic random access memory with four-bit data prefetch 13 1998
6,230,250 Synchronous memory and data processing system having a programmable burst order 5 1999
6,212,596 Synchronous memory and data processing system having a programmable burst length 2 1999
6,240,047 Synchronous dynamic random access memory with four-bit data prefetch 11 2000
 
KABUSHIKI KAISHA TOSHIBA (7)
6,249,481 Semiconductor memory device 5 1999
6,317,382 Semiconductor memory device 3 2001
6,373,785 Semiconductor memory device 3 2001
6,535,456 Semiconductor memory device 3 2002
6,654,314 Semiconductor memory device 1 2003
7,061,827 Semiconductor memory device 1 2003
7,158,444 Semiconductor memory device 0 2005
 
FUJITSU SEMICONDUCTOR LIMITED (4)
6,393,541 Data transfer memory having the function of transferring data on a system bus 11 1998
6,708,263 Data transfer memory having the function of transferring data on a system bus 1 2002
6,740,929 Semiconductor device and method for testing semiconductor device 1 2002
6,936,889 Semiconductor device and method for testing semiconductor device 4 2004
 
INTEL CORPORATION (4)
5,754,833 Method and apparatus for providing synchronous data transmission between digital devices operating at frequencies having a P/Q integer ratio 29 1997
6,114,887 Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme 6 1997
6,268,749 Core clock correction in a 2/n mode clocking scheme 17 2000
7,886,087 Split transaction protocol for a bus system 0 2010
 
RENESAS ELECTRONICS CORPORATION (4)
6,356,484 Semiconductor memory device 13 2000
6,295,238 Semiconductor memory device having a circuit for fast operation 12 2000
6,614,713 Semiconductor memory device having a circuit for fast operation 5 2001
6,762,967 Semiconductor memory device having a circuit for fast operation 6 2003
 
FUJITSU LIMITED (3)
6,157,688 Signal transmission system for transmitting signals between LSI chips, receiver circuit for use in the signal transmission system, and semiconductor memory device applying the signal transmission system 41 1997
6,377,638 SIGNAL TRANSMISSION SYSTEM FOR TRANSMITTING SIGNALS BETWEEN LSI CHIPS, RECEIVER CIRCUIT FOR USE IN THE SIGNAL TRANSMISSION SYSTEM, AND SEMICONDUCTOR MEMORY DEVICE APPLYING THE SIGNAL TRANSMISSION SYSTEM 3 2000
6,493,394 SIGNAL TRANSMISSION SYSTEM FOR TRANSMITTING SIGNALS BETWEEN LSI CHIPS, RECEIVER CIRCUIT FOR USE IN THE SIGNAL TRANSMISSION SYSTEM, AND SEMICONDUCTOR MEMORY DEVICE APPLYING THE SIGNAL TRANSMISSION SYSTEM 35 2002
 
INVENSAS CORPORATION (3)
5,729,152 Termination circuits for reduced swing signal lines and methods for operating same 48 1995
6,393,504 Dynamic address mapping and redundancy in a modular memory device 21 2000
6,754,746 Memory array with read/write methods 14 2000
 
RENESAS ELECTRONICS AMERICA, INC. (3)
5,805,873 Phase linking of output clock with master clock in memory architecture 24 1996
6,065,092 Independent and cooperative multichannel memory architecture for use with master device 140 1997
6,125,421 Independent multichannel memory architecture 41 1998
 
SUN MICROSYSTEMS, INC. (2)
7,134,035 Method for generating a synchronization signal based on the clock ratio between two clock domains for data transfer between the domains 3 2003
7,370,167 Time slicing device for shared resources and method for operating the same 0 2003
 
BLUE DANUBE LABS, INC. (1)
8,259,884 Method and system for multi-point signal generation with phase synchronized local carriers 0 2008
 
CIRRUS LOGIC, INC. (1)
5,539,428 Video font cache 18 1993
 
ELPIDA MEMORY, INC. (1)
7,095,661 Semiconductor memory module, memory system, circuit, semiconductor device, and DIMM 18 2004
 
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (1)
5,987,576 Method and apparatus for generating and distributing clock signals with minimal skew 63 1997
 
HYNIX SEMICONDUCTOR INC. (1)
7,287,143 Synchronous memory device having advanced data align circuit 2 2003
 
INTELLECTUAL VENTURES I LLC (1)
6,421,391 Transmission line for high-frequency clock 1 1997
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (1)
5,664,145 Apparatus and method for transferring data in a data storage subsystems wherein a multi-sector data transfer order is executed while a subsequent order is issued 25 1993
 
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. (1)
6,073,245 Skewing-suppressive output buffer circuit 3 1999
 
MAXTOR CORPORATION (1)
7,032,054 Method and apparatus for increasing the device count on a single ATA bus 3 2001
 
NVIDIA CORPORATION (1)
5,742,298 64 bit wide video front cache 11 1995
 
OPTI INC. (1)
7,523,245 Compact ISA-bus interface 1 2006
 
QIMONDA AG (1)
7,202,545 Memory module and method for operating a memory module 8 2004
 
ROSSLYN PRECISION LIMITED (1)
6,070,222 Synchronous memory device having identification register 14 1999
 
SAMSUNG ELECTRONICS CO., LTD. (1)
6,839,786 Information processing system with memory modules of a serial bus architecture 5 2002
 
SCANIMETRICS INC. (1)
8,362,587 Ultra high speed signal transmission/reception interconnect 0 2008
 
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (1)
7,356,656 Skew free control of a multi-block SRAM 2 2000
 
TRANSPACIFIC DIGITAL SYSTEMS, LLC (1)
5,440,754 Work station and method for transferring data between an external bus and a memory unit 12 1991
 
OTHER [CHECK PATENT PROFILE FOR ASSIGNMENT INFORMATION] (3)
8,407,395 Scalable memory system 0 2007
8,443,233 Methods and systems for failure isolation and data recovery in a configuration of series-connected semiconductor devices 0 2010
8,407,371 Apparatus and method for producing device identifiers for serially interconnected devices of mixed type 0 2011