Importance

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Abstract

An apparatus for synchronously generating a first clock signal in a first circuitry and a second clock signal in a second circuitry of a data processing system is described. A clock generating circuitry generates a global clock signal. A transmission line transfers the global clock signal from its first end to its second end and includes a midpoint between the first end and the second end. A first clock signal generation circuit is coupled at a first point between the first end and the midpoint and a second point between the midpoint and the second end. The first and second points have the same line length to the midpoint. The first clock signal generation circuit generates the first clock signal at a first timing point which is halfway between the global clock signal with a first propagation delay from the first end to the first point and the signal with a second propagation delay from the first end to the second point. A second clock signal generation circuit is coupled at a third point between the first end and the midpoint and a fourth point between the midpoint and the second end. The third and fourth points have the same line length to the midpoint. The second clock signal generation circuit generates the second clock signal at a second timing point which is halfway between the global clock signal with a third propagation delay from the first end to the third point and the signal with a fourth propagation delay from the first end to the fourth point. The first timing point is the same as the second timing point such that the first signal is synchronized with the second signal.

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First Claim