Data processing system with multiple communication buses and protocols
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United States of America Patent
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Sep 14, 1993
Grant Date -
N/A
app pub date -
Jun 21, 1989
filing date -
Jun 27, 1988
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A data processing system is presented, comprising at least one central unit (CPU), at least one central memory (MMU), and internal communication bus to which the CPU and MMU are connected, at least one peripheral unit, a control module (IOM), and an external communication bus to which the peripheral unit and the control module are connected. In this system, the IOM is also connected to the internal communication bus. The internal and external communication buses are of differing types. Within the IOM, the connection to the internal communication bus is via an internal interface device (CLM), while the connection to the external communication bus is via an external interface device (PLM). An inter-device interface (PLI), also within the IOM, connects the CLM and PLM, so as to adapt the protocols of each to the other.
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