Parallel to serial converter enabling operation at a high bit rate with slow components by latching sets of pulses following sequential delays equal to clock period
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United States of America Patent
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Sep 21, 1993
Grant Date -
N/A
app pub date -
Apr 27, 1990
filing date -
Apr 27, 1989
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A parallel to serial converter for convering incoming parallel, byte sized, data supplied at a first data rate to single bit serial data includes a shift register in which several bytes of the incoming data are stored simultaneously and thereafter serially transmitted therefrom. The parallel to serial converter includes latching devices in which the incoming data bytes are stored prior to being transferred to the shift register. Since successively arriving bytes of data are stored in successively selected ones of the latching devices, the data rate (device speed) of the latches is permitted to be only a fraction of the first data rate associated with the incoming bytes of data resulting in a fast, yet inexpensive, circuit.
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