Parallel digital processor including lateral transfer buses with interrupt switches to form bus interconnection segments
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Sep 21, 1993
Issued Date -
N/A
app pub date -
Feb 9, 1990
filing date -
Feb 25, 1985
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A digital computer system including a large number of parallel processing modules (PPM's). Each PPM includes an arithmetic logic unit (ALU), an instruction decoder, and internal bus switching. The main memory is organized in columns and rows with a separate column for each PPM port. Each PPM preferably includes at least three ports to permit parallel transfer of instructions and data to the PPM's. The ports of the PPM's are also connected to segmented lateral transfer buses which operate in conjunction with the internal bus switching of the PPM's to permit tandem ALU operation.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully