Method for the hierarchical comparison of schematics and layouts of electronic components
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United States of America Patent
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Sep 28, 1993
Grant Date -
N/A
app pub date -
Apr 10, 1991
filing date -
Apr 10, 1991
priority date (Note) -
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Abstract
The present invention takes advantage of the hierarchical nature of the design to perform a hierarchical comparison on as many blocks and sub-blocks which can be matched between the layout and the logic design. Because the internal connections were previously verified when the first occurrence of the block was compared, repetition of lengthy comparisons of multiple occurrences of the same blocks in the designs is avoided and subsequent comparisons are performed simply by comparing the input and output connections to the block.
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