Importance

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Abstract

In a memory device, if there is a defective column among the memory cell columns in the memory cell array, all of the bit lines sharing the same I/O data lines as such a defective column are separated from the I/O data line regardless of the column address, and instead a group of spare bit lines disposed corresponding to each column address and selected according to the column addresses is electrically connected to the I/O data line. In this structure, the bit lines are disposed by dividing into corresponding I/O data line, and if there are defects extending in two or more columns, as long as they are within a block of the same I/O data line, all of the defective memory cells can be replaced by the memory cells in the spare column. Therefore, while minimizing the increase of chip area and lowering of operating speed in the multiple-bit organized memories, a redundancy circuit having a high defect repair efficiency may be realized.

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First Claim