Lock detection for a phase lock loop
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United States of America Patent
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Oct 26, 1993
Grant Date -
N/A
app pub date -
May 3, 1991
filing date -
May 3, 1991
priority date (Note) -
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status (Latency Note)
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Abstract
A phase lock loop monitors a first digital signal and generates a second digital signal operating substantially at frequency and in-phase with the first digital signal. The first and second digital signal are applied to a lock detection circuit for generating a first digital output signal having a first logic state from a mutually exclusive combination of the first and second digital signals. The first logic state of the first digital output signal is compared with a time slot window formed by a control signal for generating a true lock detection signal when the first logic state of the first digital output signal occurs within the time slot window and a false lock detection signal when the first logic state of the first digital output signal occurs outside the time slot window.
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