Narrow radius tips for high voltage semiconductor devices with interdigitated source and drain electrodes

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United States of America Patent

PATENT NO 5258636
SERIAL NO

07808024

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Abstract

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A field effect transistor (FET), according to the present invention, comprises a source and drain pair of electrodes having non-uniform charge distributions between them, such as results from small radius tips, and has a gate and channel structure that exists only between points of the source and drain pair that have the less intense charge distributions, e.g., areas not involving any small radius tips. The gate and channel structure is such that, given the non-uniform charge distributions between the source and drain pair of electrodes, the electric field is reduced around the tip by eliminating the n-well junction near the source-drain fingertips.

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Patent Owner(s)

  • POWER INTEGRATIONS, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Busse, Robert W Mountain View, CA 4 159
Rumennik, Vladimir Los Altos, CA 23 1325

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