Semiconductor memory with separate time-out control for read and write operations
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United States of America Patent
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-
Nov 2, 1993
Grant Date -
N/A
app pub date -
Dec 14, 1990
filing date -
Dec 14, 1990
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A read/write memory having timed-out control of certain of its peripheral circuitry is disclosed. The control circuit for controlling the time at which time-out is to occur includes two delay stages of different lengths. The shorter delay stage is used to define the time-out in a read operation, and the longer delay stage is used to define the time-out in a write operation, since a read operation can generally be accomplished sooner than a write operation. Enabling of the periphery is controlled by an address transition detection circuit, and by a data transition detection circuit. The circuit includes a short path by which enabling of the periphery is performed responsive to a data transition in the absence of an address transition, in order to perform a late write operation.
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