Method for substantially eliminating hold time violations in implementing high speed logic circuits or the like
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United States of America Patent
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Nov 2, 1993
Issued Date -
N/A
app pub date -
Aug 20, 1991
filing date -
Apr 18, 1990
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method is provided for eliminating hold time violations in implementing high-speed logic circuits specified in circuit configuration data includes the steps of providing a synchronizer flip-flop device or latch corresponding to every flip-flop device or latch specified in the circuit configuration data. The synchronizer flip-flop is provided immediately upstream in the data path from its corresponding original user flip-flop device. A predetermined amount of delay is added to the user's original clock and data signals. A synchronizing clock signal generator provides a delayed synchronizer clock for each master clock in the circuit which is provided to each user flip flop.
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