Importance

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Abstract

A video processor, having an image data bus across which image data can be transmitted, is provided. The video processor includes a memory section for storing image data transmitted thereto, the memory section being coupled with the image bus. The video processor further includes first and second buffering devices respectively coupled with the image bus. The first buffering device is capable of buffering image data transmitted from the input device to the storing means, while the second buffering device is capable of buffering image data transmitted from the memory section to the output device. Each of the first and second buffering devices is adapted to generate a request signal when seeking access to the image bus. The first and second buffering devices are coupled respectively with a device for arbitrating which of the first and second buffering devices is enabled to access the image data bus to transfer image data with the memory section when the arbitrating device concurrently receives request signals from the first and second buffering devices.

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First Claim