Sequence control apparatus for producing output signals in synchronous with a consistent delay from rising or falling edge of clock input signal
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United States of America Patent
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Nov 9, 1993
Grant Date -
N/A
app pub date -
Jul 26, 1990
filing date -
Jul 26, 1990
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
Sequence control apparatus provides a plurality of output signals selectively based upon either the rising or falling edge of a clock signal. The apparatus includes a plurality of groups of bistable devices such as flip flops. In each group, half of the flip flops are triggered by the rising edge of a clock pulse and the other half of the flip flops are triggered by the falling edge. The outputs of these flip flops are coupled to a series of gates, which in turn are controlled by logic input select signals to provide output signals which may be used, for example, for memory control purposes. The output signal from one group of flip flops is provided as an input signal for the next group.
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