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Abstract

A processor (10) is disclosed which uses a B-spline interpolator (14) to produce a plurality of zero-level spline coefficients c.sup.0 (n). This set of coefficients may be fed to a B-spline generator (16) to produce an approximation of the input signal, and/or may be multiplied by a set of coefficients Bn to produce a set of first-level wavelet coefficients d.sup.-1 (n). The zero-level spline coefficients are also used to create first-level spline coefficients c.sup.-1 (n). The first-level spline and wavelet coefficient c.sup.-1 (n) and d.sup.-1 (n) may be submitted to a respective B-spline generator (22) or B-wavelet generator (24) to produce a first-level spline signal components and a first-level wavelet signal component for extraction of data from the original signal. The signal may in a similar fashion be decomposed to any level of resolution desired. The signal components may then be processed, and an improved signal then reassembled from the last-level spline and the processed wavelet signals. Novel spline and wavelet generators are also disclosed.

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First Claim