High performance architecture for image processing

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United States of America Patent

PATENT NO 5262968
SERIAL NO

07904315

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Abstract

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The logical computer architecture is specifically designed for image processing, and other related computations. The architecture is a data flow concept comprising three tightly coupled components: a spatial configuration processor, a point-wise operation processor, and a accumulation operation processor. The data flow and image processing operations are directed by the control buffer and pipelined to each of the three processing components. The image processing operations are defined by an image algebra capable of describing all common image-to-image transformations. The merit of this architectural design is how elegantly it handles the natural decomposition of algebraic functions into spatially distributed, point-wise operations. The effect of this particular decomposition allows convolution to be computed strictly as a function of the number of elements in the template (mask, filter, etc.) instead of the number of pixels in the image. Thus, a substantial increase in throughput is realized. The logical architecture may take any number of physical forms, including a hybrid electro-optical implementation, and an all digital implementation. The potential utility of this architectural design lies in its ability to control all the arithmetic and logic operations of the image algebra's generalized matrix product. This is the most powerful fundamental formulation in the algebra, thus allowing a wide range of applications.

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Patent Owner(s)

  • THE UNITED STATES OF AMERICA AS REPRESENTED BY THE SECRETARY OF THE AIR FORCE

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Coffield, Patrick C Shalimar, FL 2 40

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