Integrated circuit logic functions simulator for selectively connected series of preprogrammed PLA devices using generated sequence of address signals being provided between simulated clock cycles
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United States of America Patent
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Nov 16, 1993
Grant Date -
N/A
app pub date -
Feb 19, 1991
filing date -
Mar 8, 1990
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A hardware simulator comprises a plurality of interconnected programmable logic devices (20) which are connected via a data bus (22) and a control bus (24). Address signals on control bus (24) are read by an interconnect logic block (18) associated with each device to selectively link the output latches and input latches of the devices (20) to the data bus (22). Accordingly, a series of signal transfers is carried out between the devices simulating the hardware. The interconnect logic blocks may be programmed to provide whatever connections between devices are required.
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