Testing timing parameters of high speed integrated circuit devices
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United States of America Patent
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Dec 7, 1993
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N/A
app pub date -
Jun 5, 1992
filing date -
Jun 5, 1992
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Abstract
A method and apparatus for testing input and output parameters for high speed integrated circuit devices. An integrated circuit tester generates a receive clock and a transmit clock using a pair of pre-selected output pins. The integrated circuit tester adjusts the phase relation between the transmit clock and the receive clock. Special circuitry within the device under test compares input and output data to detect errors.
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