Bit serial floating point parallel processing system and method
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United States of America Patent
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Dec 7, 1993
Issued Date -
N/A
app pub date -
Sep 25, 1992
filing date -
Jun 6, 1988
priority date (Note) -
Expired
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Abstract
A system and method for floating point computations involving matrices or vectors includes a plurality of identical processing units connected to a linear chain with direct data communication links between adjacent processing units. Each such processor is also connected to its own private memory. A sequence of instructions is sent by a controller to all floating point processing units and their associated memories whereby all processing units in the chain receive the same instruction and all memories receive the same address at any given cycle in the instruction sequence. Each processing unit internally handles floating point operations such as normalization, sign changes, and multiplication in a bit serial manner.
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