Method and apparatus for negating an operand
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United States of America Patent
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-
Dec 7, 1993
Grant Date -
N/A
app pub date -
Aug 30, 1991
filing date -
Aug 30, 1991
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A multiplier system 12 is disclosed which provides for the negation of an operand stored in an operand register 14. When a negative operand must be loaded into a partial product generator 26, a carry bit is selectively generated in carry logic 44 and a selected bit or bits within the partial product is set to zero. During a subsequent pass through the multiplier system 12, a bit is added at a block 46 to provide for the addition of the required quantity for the negation of the operand.
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