Synchronous digital signal to asynchronous digital signal desynchronizer
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United States of America Patent
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Dec 7, 1993
Issued Date -
N/A
app pub date -
Feb 26, 1993
filing date -
Jul 8, 1991
priority date (Note) -
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Abstract
Improved jitter performance is realized in a desynchronizer for obtaining an asynchronous signal, e.g., a CEPT-4 signal, from a received synchronous signal, e.g., a SDH STM-1 signal. The improved jitter performance results from employing a unique gap generator which causes gaps in a received data signal to be spread regularly in time, and allows for almost continuous control by numerical techniques of the phase of a smooth output clock being generated. Phase control is obtained by employing a filtered version of the difference between the actual number of data bits in the received digital signal and the expected nominal number.
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