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Abstract

An event-driven logic simulator provides for future evaluation events. Evaluation latencies are assigned to respective inputs of components based on component type. At least some of these latencies are positive and finite. When a signal status event specifies a change at an input associated with a positive latency, the function for the component is not evaluated at the present time. Instead, the evaluation is postponed to a future time equal to the present time plus the assigned latency. The evaluation is thus latent until the scheduled time becomes present. When multiple evaluation events are indicated for a common component output, a queue manager resolves the conflicts by discarding all but one of the evaluation events for that output. This approach minimizes redundant and superfluous evaluations during circuit simulation.

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First Claim