Clock signal latency elimination network
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United States of America Patent
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Dec 21, 1993
Grant Date -
N/A
app pub date -
Sep 20, 1991
filing date -
Sep 20, 1991
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A process independent digital clock signal timing network is described for generating a chip clock substantially in phase with and offset by one cycle from an input clock signal. The timing network determines the delay experienced by a clock signal passing through a predetermined internal clock circuit on the chip and pregates the internal clock circuit by an amount equivalent to the determined delay such that the chip clock signal output from the internal clock circuitry lags the external clock signal input to the semiconductor chip by one cycle. Various timing network embodiments are described and claimed.
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