Method for forming metallization in an integrated circuit
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United States of America Patent
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Jan 4, 1994
Grant Date -
N/A
app pub date -
Mar 1, 1993
filing date -
Mar 1, 1993
priority date (Note) -
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Abstract
Metallization having a self-aligned diffusion barrier or seed layer is formed in an integrated circuit. In one embodiment of the invention, a sacrificial material (20) is used to define a seed layer (24). A dielectric layer (26) is then formed and the sacrificial material (20) is subsequently removed to expose the underlying seed layer (24). A conductive layer of material (32), such as copper, is then selectively deposited onto the seed layer (24). Because the diffusion barrier or seed layer is self-aligned the metal to metal spacing in an integrated circuit may be reduced. Therefore, integrated circuits having high device packing densities can be fabricated.
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