Multilayer interconnect system for an area array interconnection using solid state diffusion

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United States of America Patent

PATENT NO 5276955
SERIAL NO

07868531

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Abstract

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A method and apparatus for manufacturing large area multilayer interconnects for electronic substrates and circuit boards uses high density area array interconnections that are created by solid state diffusion. Two or more pretested subsections are electrically and mechanically joined together to simultaneously form a multilayer substrate without employing a flow-type connection where the conductive interconnect material is entirely in a liquid phase at some point during the joining process. Each substrate is comprised of a planar dielectric substrate having a plurality of conductive layers. On at least one surface of the substrate a conductive pad lay is formed having a plurality of interconnect pads. The interconnect pads are positioned at a uniform height above the surface of the dielectric substrate and include a base metal layer, a top metal layer with at least one of the conductive pad layers have a donor metal disposed on top of the top metal layer. When the conductive pad layers of two or more subsections are aligned and stacked together, the interconnect pads can be mechanically and electrically joined together using solid state diffusion to join the donor metal layer and the top metal layer to form an area array interconnection without bonding the surrounding dielectric substrate.

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Patent Owner(s)

Patent OwnerAddress
SILICON GRAPHICS INTERNATIONAL CORP46600 LANDING PARKWAY FREMONT CA 94538-6420

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Gorrell, Robin E Eau Claire, WI 21 372
Leaf, Michael R Hammond, WI 6 130
Leong, Jimmy Eau Claire, WI 5 226
Noddin, David B Eau Claire, WI 19 831
Petefish, William G Eau Claire, WI 6 430
Piper, Boydd Eau Claire, WI 3 75
Stumpe, Kevin L Altoona, WI 1 64
Swamy, Deepak N Eau Claire, WI 7 248

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