System for providing gapless data transfer from page-mode dynamic random access memories
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United States of America Patent
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Jan 11, 1994
Grant Date -
N/A
app pub date -
Aug 31, 1990
filing date -
Aug 31, 1990
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A programmable memory controller generates address and control signal information associated with a word of data which is desired to be transferred first from dynamic random access memory (DRAM) modules. The generated information specifically assists memory support circuitry interfacing with page mode DRAMs. This information is normally provided to the memory support circuitry just before selection of the staring word from a fetch line data buffer. Memory latency, gaps in data transfer, can be reduced when this information is available to the support circuitry as it drives column address and/or column address strobe (CAS) signals to the DRAMs.
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