Method for testing semiconductor integrated circuits soldered to boards and use of a transistor tester for this method
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United States of America Patent
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Jan 18, 1994
Grant Date -
N/A
app pub date -
Mar 23, 1992
filing date -
Mar 30, 1991
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A method for testing a semiconductor integrated circuit soldered into a printed circuit board makes use of the existence of parasitic transistors which occur on integrated circuits having diodes formed thereon. The method includes applying a voltage across the pins of the integrated circuit to be tested, measuring currents resulting from the voltage applied across the pins of the integrated circuit, connecting a transistor tester to selected pins of the integrated circuit, and determining typical control or switching characteristics of a parasitic transistor (1T, 2T) of the semiconducting integrated circuit (IC1, IC2). A commercial transistor tester is usable to perform the method.
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