Floating gate nonvolatile memory with configurable erasure blocks
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United States of America Patent
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Jan 18, 1994
Grant Date -
N/A
app pub date -
Jun 19, 1992
filing date -
Jun 19, 1992
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Abstract
A nonvolatile memory includes a first block and a second block. The first block comprises a first memory cell and a first source line coupled to a source of the first memory cell. The second block comprises a second memory cell and a second source line coupled to a source of the second memory cell. A first source switch is coupled to the first source line for selectively coupling a first potential, a second potential, and a third potential to the first source line. The second potential has a voltage intermediate between the first potential and the third potential. A second source switch is coupled to the second source line for selectively coupling one of the first, second, and third potentials to the second source line. A block select circuit receives a block address for selecting one of the first and second source switches to couple one of the first, second, and third potentials to its respective one of the first and second source lines. A configuration cell is coupled to the block select circuit for configuring block operations of the first and second blocks. When the configuration cell is in a first voltage state, the configuration cell causes the block select circuit to separately select one of the first and second source switches depending upon the address received. When the configuration cell is in a second voltage state, the configuration cell causes the block select circuit to collectively select the first and second source switches.
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Patent Owner(s)
- INTEL CORPORATION
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Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Hazen, Peter K | Sacramento, CA | 19 | 664 |
Sweha, Sherif R B | El Dorado Hills, CA | 4 | 176 |
Talreja, Sanjay S | Citrus Heights, CA | 19 | 1037 |
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Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
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