Scalable processor to processor and processor-to-I/O interconnection network and method for parallel processing arrays
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United States of America Patent
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Jan 18, 1994
Grant Date -
N/A
app pub date -
Jan 5, 1990
filing date -
Jan 5, 1990
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A massively parallel computer system is disclosed having a global router network in which pipeline registers are spatially distributed to increase the messaging speed of the global router network. The global router network includes an expansion tap for processor to I/O messaging so that I/O messaging bandwidth matches interprocessor messaging bandwidth. A route-opening message packet includes protocol bits which are treated homogeneously with steering bits. The route-opening packet further includes redundant address bits for imparting a multiple-crossbars personality to router chips within the global router network. A structure and method for spatially supporting the processors of the massively parallel system and the global router network are also disclosed.
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