Reduced-voltage NMOS output driver

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United States of America Patent

PATENT NO 5281869
SERIAL NO

07907402

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A tri-state output buffer circuit employs N-channel pull-up and pull-down transistors, with another N-channel transistor connected between the pull-up and pull-down transistors and having its gate connected to the low-voltage supply. An output node at one side of the pull-up transistor may be driven to a voltage higher than the supply, without subjecting the pull-up to hot-carrier effects or other deleterious effects of over-voltage. When in the high-impedance output state, the gate of the pull-up is shorted to an intermediate node which is the drain of the pull-down transistor, using a P-channel and an N-channel transistor responsive to the logic input. The voltage on the gate of the pull-up transistor is allowed to track the output up to the reduced voltage supply minus V.sub.TN when in the high-impedance state, by tying the gate of the pull-up transistor to the intermediate node; this prevents damage to the pull-up due to hot-carrier effects.

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Patent Owner(s)

Patent OwnerAddress
HEWLETT-PACKARD DEVELOPMENT COMPANY L P11445 COMPAQ CENTER DRIVE WEST HOUSTON TX 77070

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lundberg, James R Austin, TX 91 1583

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