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Abstract

The disclosed adaptive finite impulse response (FIR) digital filter architecture computes tap coefficient updates in parallel with and simultaneously with the computation of the filter output at each iteration. The filter includes a filter output processor (206) and a tap update processor (212) which respectively process, in parallel, the filter output and the coefficient updates for a subsequent iteration. The filter output processor and the tap update processor form their respective outputs at each iteration from input signal values at previous iterations stored in a filter input memory (203) and from tap coefficients stored in a filter taps memory (205). In even-numbered iterations only the even-numbered taps are updated and in odd-numbered iterations only the odd-numbered taps are updated. At every iteration, in forming the filter output and the even or odd tap updates, the previous inputs and tap coefficients are accessed in a pattern that requires that they be fetched only once from their respective memories.

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