Importance

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Abstract

The specification discloses preferred circuits and methods for performing a block write in a video random access memory circuit (VRAM). The VRAM has a plurality of memory registers, an address bus, and a data bus. The VRAM also has a multiple write register circuit with a plurality of write registers. During write register load cycles, data is written from the data bus to individual write registers which are specified by addresses received on the address bus. During a block write cycle, data is written from an individual write register to a selected block of memory registers; the block having a predefined number of memory registers within a row. The block of memory registers is specified by memory register base address received on the address bus. The memory register base address is the address of the first memory register in the block of memory registers. An individual write register from which data is written to the block of memory registers is selected during a block write cycle by an address received on the data bus.

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First Claim